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16bit_booth_multiplier_STG
- verilog程序，实现两个16bit数乘法，采用booth算法，基于状态机实现，分层次为datapath和controller两个子模块，testBench测试通过-verilog procedures, two 16bit multiplication, the algorithm used booth. Based on the state machine achieved at different levels for datapath controller and two sub-mo
multiply
- 这是我用verilog hdl语言写的浮点乘法器,用的是基4的booth算法,对于部分积使用了5-2压缩和3-2压缩,欢迎大家指点,也欢迎大家把它改成流水线以提高速度.
BOOTH2
- verilog booh multiplier-booth
dsa_report
- Verilog code for the synthesis of an 8-bit booth multiplier
BBooth
- 基verilog 布斯乘法器 4位位宽，本人不才，仅做参考-Booth multiplier based verilog
24x24-booth
- 可用的24位x24位的booth乘法器的verilog代码-24X24 booth muplily
booth
- booth multiplier in verilog
MIPS_final-version
- 以Verilog所撰寫的Booth’s Algorithm Multiplier，可加到NiosII CPU之上，完成一道NiosII CPU的新指令。-Written by Verilog Booth,' s Algorithm Multiplier can be added to the above NiosII CPU to complete a the Nios II CPU command.
pipeline
- 以Verilog撰寫而成的Booth’s Algorithm Multiplier，並以Pipeline方式實現。-Written in the Verilog Booth' s Algorithm Multiplier, and the Pipeline way.
booth
- this implementation of booth multiplier. by this we can implement booth mul in vhdl. we can also implement in verilog.-this is implementation of booth multiplier. by this we can implement booth mul in vhdl. we can also implement in verilog.
4-Booth
- booth algorithm by verilog
booth-16_16-multiplier
- 由verilog编写的利用booth编码的16*16有符号乘法器的代码，没有pipeline-a 16*16 multiplier with booth coding by verilog
Verilog-code-for-multiplier
- VERILOG CODE FOR 16 BIT MULTIPLIER USING MODIFIED BOOTH ALGORITHM
mult-64bit-booth.txt
- 64位booth乘法器，verilog HDL， zip文件，modelsim测试通过-64 booth multiplier, verilog HDL, zip files, modelsim test
booth-mutiplier
- booth乘法器的verilog实现及仿真。 内含verilog源码和modelisim仿真源码，清晰的实现了硬件乘法器，代码注释清晰-booth multiplier verilog verilog implementation and simulation contains the source code and modelisim simulation code, clear notes
4booth_multiplie_module_2
- 采用Verilog对Booth算法乘法器的改进，对想学习乘法器的会有很大的帮助。-Improved algorithm using Verilog Booth multiplier, multiplier want to learn to have a lot of help.
booth.tar
- Booth algorithm multiplier this project design booth multiplier by verilog language. you can open it by ISE and simulate.
Minor-1
- code for "booth multiplier" using verilog
16 bit signed number multiplier
- 16位有符号数乘法器，使用Booth编码和华莱士树，提供程序源文件和测试文件(The 16 bit signed multiplier uses Booth encoding and Wallace tree to provide source files and test files.)
multiplier
- Booth乘法器是属于位操作乘法器，采用流水线结构实现(The Booth multiplier is a bit-operated multiplier that is implemented in a pipeline structure.)